File:12-input OR gate via NOR and NAND gates.svg

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An implementation of a 12-input OR gate via NOR and NAND gates

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Description
English: An implementation of a cascaded implementation, which used de Morgan's laws to convert or(or(a,b,c),or(d,e,f),or(g,h,i)) into nand(nor(a,b,c),nor(d,e,f),nor(g,h,i)). This is more efficient on logic families such as CMOS, NMOS or TTL where an OR gate needs to be synthesized from a NOR gate and an inverter.
Date
Source Own work
Author Trex4321

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Date/TimeThumbnailDimensionsUserComment
current19:26, 4 February 2024Thumbnail for version as of 19:26, 4 February 2024257 × 162 (5 KB)Trex4321 (talk | contribs)Uploaded own work with UploadWizard

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