File:AVX registers.svg
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| Description | Registers introduced with AVX (Advanced Vector Extensions). SSE registers are aliased as lower parts of YMM0..YMM7. Registers YMM8..YMM15 are available when the processor works in 64-bit mode. |
| Date | |
| Source | Own work |
| Author | Wojciech Muła |
| Permission (Reusing this file) |
public domain |
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I, the copyright holder of this work, release this work into the public domain. This applies worldwide. In some countries this may not be legally possible; if so: I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law. |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 20:52, 1 June 2012 | | 330 × 350 (33 KB) | XAVeRY (talk | contribs) | The previous drawing was a bit wrong. The lower halves of all YMM registers are always aliased to their respective XMM registers, including those available only in 64-bit mode (8-15). Reference : Intel Basic Architecture, Chapter 13.1.1 "256-Bit Wide S... |
| 13:32, 7 April 2008 |  | 330 × 350 (25 KB) | Wojciech mula (talk | contribs) | align labels | |
| 12:41, 6 April 2008 |  | 330 × 350 (27 KB) | Wojciech mula (talk | contribs) | fixed | |
| 12:35, 6 April 2008 |  | 350 × 420 (28 KB) | Wojciech mula (talk | contribs) | {{Information |Description=Registers introducted with AVX (Advanced Vector Extensions). SSE registers are aliased as lower parts of YMM0..YMM7. Registers YMM8..YMM15 are available when processor work in 64-bit mode. |Source=self-made |Date= |Author= [[U |
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