Category:Digital logic

Subcategories

This category has the following 3 subcategories, out of 3 total.

Media in category "Digital logic"

The following 48 files are in this category, out of 48 total.

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  Animated diode logic encoder.gif 320 × 972; 83 KB
  
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  Band gap vs E.jpg 1,000 × 750; 67 KB
  
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  Binary Multiplier.pdf 1,500 × 1,125, 8 pages; 673 KB
  
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  Bundled data protocol.svg 700 × 400; 5 KB
  
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  CML line.svg 230 × 95; 9 KB
  
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  CML output stage.svg 400 × 460; 17 KB
  
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  Cmos impurity profile-en.svg 926 × 355; 3 KB
  
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  Cmos impurity profile-ru.svg 926 × 355; 2 KB
  
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  Cmos impurity profile.PNG 722 × 300; 4 KB
  
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  Communication asynchrone.svg 550 × 300; 6 KB
  
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  Comparator.png 324 × 677; 10 KB
  
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  Compatibilità tra porte logiche.png 338 × 381; 2 KB
  
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  D-element multiple use circuit.png 480 × 234; 5 KB
  
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  David cell.png 333 × 218; 4 KB
  
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  DominoLogic-LaTeX.png 600 × 703; 33 KB
  
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  Dual-rail protocol.svg 700 × 400; 4 KB
  
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  ECL structure 1000.jpg 1,000 × 714; 106 KB
  
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  Esempio di circuiti a più ingressi.png 390 × 259; 2 KB
  
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  Example circuitry.jpg 467 × 982; 86 KB
  
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  FPGAEtShields2.png 582 × 237; 33 KB
  
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  FPGAEtShields3.png 677 × 536; 95 KB
  
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  FPGAEtShields4.png 712 × 721; 78 KB
  
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  FPGAEtShields5.png 640 × 203; 42 KB
  
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  FPGAEtShields7.png 678 × 544; 108 KB
  
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  FPGAEtShields8.png 683 × 417; 395 KB
  
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  FPGAEtShields9.png 681 × 305; 59 KB
  
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  Freq. devider with RS.jpg 986 × 372; 46 KB
  
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  Graycode to Binary.PNG 930 × 285; 11 KB
  
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  HCSL output stage.svg 390 × 540; 83 KB
  
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  Ideal transition times.png 333 × 225; 1 KB
  
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  LUT.png 709 × 365; 188 KB
  
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  Negative-Positive Logic (AND gate, OR gate).PNG 922 × 243; 22 KB
  
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  Pipeline sync-async.svg 1,050 × 1,200; 15 KB
  
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  PMOS-inverter.svg 390 × 620; 16 KB
  
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  PMOS-NAND-gate.svg 461 × 673; 24 KB
  
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  PMOS-NOR-gate.svg 461 × 780; 23 KB
  
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  Propagation times.png 212 × 227; 1 KB
  
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  Proposed ENAND Symbol.svg 1,066 × 419; 4 KB
  
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  Protocole 3 états.svg 247 × 210; 10 KB
  
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  Protocole 4 états.svg 280 × 250; 11 KB
  
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  Real transition times.png 333 × 225; 2 KB
  
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  Single track protocols.svg 700 × 800; 7 KB
  
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  Td4bfig2.png 275 × 98; 4 KB
  
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  Td4bfig3.png 247 × 129; 4 KB
  
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  Td4bfig4.png 183 × 105; 6 KB
  
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  Transmission gate equivalent circuit.png 429 × 192; 2 KB
  
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  বৈদ্যুতিক উপমা অ্যান্ড সার্কিট.jpg 3,472 × 4,640; 5.19 MB
  
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  負帰還増幅回路の原理図.svg 550 × 350; 52 KB