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File:3 bit shif tregister.jpg

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Description
English: A three-bit serial-in serial-out (SISO) shift register. This circuit introduces a 3-cycle delay in the data line.
Date
Source Lecturer's notes
Author Dr. Ray Eaton
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Public domain This image of simple geometry is ineligible for copyright and therefore in the public domain, because it consists entirely of information that is common property and contains no original authorship.
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Date/TimeThumbnailDimensionsUserComment
current13:31, 23 April 2008Thumbnail for version as of 13:31, 23 April 2008454 × 164 (8 KB)JFonseka (talk | contribs){{Information |Description=Common circuit diagram |Source=Lecturer's notes |Date=23/04/2008 |Author=Dr. Ray Eaton |Permission=Fair use |other_versions= }}

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