File:Altera-cyclone-1-fpga-Si-HD.jpg
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| Description |
English: The Altera Cyclone EP1C3 is the smallest 1st generation FPGA from Altera. It has 2910 LE, 1 PLL and 58.5 kibibits of memory (13 M4K blocks, 128x36 bits each). Polysilicon level showing that each M4K block is subdivided into 2 halves (26 'rectangles' total in 2 columns). The array of logical elements is non-symmetrical. On the right side of the array in the middle is a PLL. Half of the die area is occupied by peripherals to support a variety of input-output (IO) standards. |
| Date | |
| Source | http://zeptobars.ru/en/read/Altera-Cyclone-EP1C3 |
| Author | ZeptoBars |
| Permission (Reusing this file) |
"All die-shots published on this site are licensed under a Creative Commons Attribution 3.0 Unported License." [1] |
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This file is licensed under the Creative Commons Attribution 3.0 Unported license.
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- Under the following conditions:
- attribution – You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
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This file, which was originally posted to
http://zeptobars.ru/en/read/Altera-Cyclone-EP1C3, was reviewed on 8 August 2019 by reviewer Meisam, who confirmed that it was available there under the stated license on that date.
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 12:51, 18 June 2014 | | 5,744 × 5,440 (18.07 MB) | Dhx1 (talk | contribs) |
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