File:CPU block diagram.svg
Size of this PNG preview of this SVG file: 260 × 360 pixels. Other resolutions: 173 × 240 pixels | 347 × 480 pixels | 555 × 768 pixels | 739 × 1,024 pixels | 1,479 × 2,048 pixels.
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Summary
editDescriptionCPU block diagram.svg |
English: Block diagram of a hypothetical simple CPU, showing instruction fetch, decode, data registers, ALU, and memory interface, and major relationships.
Español: Diagrama de una hipotética y simple "Unidad Central de Proceso" (CPU), mostrando la captura de una instrucción y su decodificación, así como los registros de datos, la "Unidad Aritmético-Lógica" (ALU), la interfaz de memoria, y otras relaciones.
Italiano: Diagramma a blocchi semplificato di una CPU, dall'alto: il ricevitore di istruzioni, il decodificatore, i registri dati, l'unità aritmetico-logica (ALU); a destra è rappresentata l'interfaccia alla memoria. |
Date | 1 June 2006 (original upload date) |
Source | Own work based on: CPU block diagram.png |
Author |
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SVG development InfoField | This diagram was created with Inkscape. This diagram uses translateable embedded text. |
Licensing
editThis file is licensed under the Creative Commons Attribution-Share Alike 3.0 Unported license. Subject to disclaimers. | ||
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This licensing tag was added to this file as part of the GFDL licensing update.http://creativecommons.org/licenses/by-sa/3.0/CC BY-SA 3.0Creative Commons Attribution-Share Alike 3.0truetrue |
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled GNU Free Documentation License. Subject to disclaimers.http://www.gnu.org/copyleft/fdl.htmlGFDLGNU Free Documentation Licensetruetrue |
Original upload log
editThe original description page was here. All following user names refer to en.wikipedia.
- 2007-04-12 03:48 R. S. Shaw 260×360× (10716 bytes) Revision removing rounded corners from ALU
- 2006-06-01 03:52 Booyabazooka 260×360× (12541 bytes) :''This vector image was converted from the original raster version: [[:Image:CPU block diagram.png]]'' ==Summary== Block diagram of a hypothetical simple CPU, showing instruction fetch, decode, data registers, ALU, and memory interface, and major relati
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Date/Time | Thumbnail | Dimensions | User | Comment | |
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current | 14:32, 13 October 2012 | 260 × 360 (10 KB) | OgreBot (talk | contribs) | (BOT): Uploading old version of file from en.wikipedia; originally uploaded on 2007-04-12 03:48:00 by R. S. Shaw | |
12:47, 12 November 2006 | 260 × 360 (12 KB) | German (talk | contribs) | {{Information |Description=Block diagram of a hypothetical simple CPU, showing instruction fetch, decode, data registers, ALU, and memory interface, and major relationships. |Source=http://en.wikipedia.org/wiki/Image:CPU_block_diagram.svg |Date=2006-06-01 |
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Width | 260 |
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Height | 360 |