File:NOR gate layout.png
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| Description |
Shows a CMOS implementation of a NOR gate. Also used at http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/ |
| Date | 20 November 2009 (original upload date) |
| Source | No machine-readable source provided. Own work assumed (based on copyright claims). |
| Author | No machine-readable author provided. Miquel puig assumed (based on copyright claims). |
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I, the copyright holder of this work, release this work into the public domain. This applies worldwide. In some countries this may not be legally possible; if so: I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law. |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 12:41, 20 November 2009 | | 600 × 433 (22 KB) | Miquel puig (talk | contribs) | == Summary == Shows a CMOS implementation of a NOR gate. Also used at http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/ == Licensing == {{PD-self|date=November 2007}} Category:Logic Category:Logic gates |
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