File talk:Full-adder logic diagram.svg
Latest comment: 6 years ago by 220.237.123.153
This circuit fails (at least in Logisim) if A and Cin are on. Cout should be 1, but is 0. An additional AND gate between A and Cin is needed before the OR gate. --220.237.123.153 06:15, 19 August 2017 (UTC)
