File:A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation (IA acmosvlsiicforre1094539739).pdf

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A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation   (Wikidata search (Cirrus search) Wikidata query (SPARQL)  Create new Wikidata item based on this file)
Author
Richstein, James K.
image of artwork listed in title parameter on this page
Title
A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation
Publisher
Monterey, California. Naval Postgraduate School
Description

Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straight forward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator has been designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi- opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two- dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display have been combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns.


Subjects: VLSI (very large scsale integration) design; MAGIC; CMOS; Optics; Image processing
Language English
Publication date December 1993
publication_date QS:P577,+1993-12-00T00:00:00Z/10
Current location
IA Collections: navalpostgraduateschoollibrary; fedlink
Accession number
acmosvlsiicforre1094539739
Source
Internet Archive identifier: acmosvlsiicforre1094539739
https://archive.org/download/acmosvlsiicforre1094539739/acmosvlsiicforre1094539739.pdf
Permission
(Reusing this file)
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.

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Public domain
This work is in the public domain in the United States because it is a work prepared by an officer or employee of the United States Government as part of that person’s official duties under the terms of Title 17, Chapter 1, Section 105 of the US Code. Note: This only applies to original works of the Federal Government and not to the work of any individual U.S. state, territory, commonwealth, county, municipality, or any other subdivision. This template also does not apply to postage stamp designs published by the United States Postal Service since 1978. (See § 313.6(C)(1) of Compendium of U.S. Copyright Office Practices). It also does not apply to certain US coins; see The US Mint Terms of Use.

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current20:59, 13 July 2020Thumbnail for version as of 20:59, 13 July 20201,275 × 1,650, 94 pages (3.17 MB) (talk | contribs)FEDLINK - United States Federal Collection acmosvlsiicforre1094539739 (User talk:Fæ/IA books#Fork8) (batch 1993-2020 #5143)

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